Embodiments of the present invention relate to integrated circuits and the processing for the manufacture of semiconductor devices. In particular, embodiments of the invention provide a method and device for varactors used in integrated circuits. More particularly, embodiments of the invention provide a method and device for device layout to reduce series resistance and parasitic capacitance. Merely by way of example, the invention has been applied to achieving high quality factor (Q) of a variable capacitor for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuit layout of devices sensitive to parasitic resistance and capacitance, such as resistors, inductors, and transistors, etc.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is variable capacitors, also known as varactors, used for the manufacture of integrated circuits in a cost effective and efficient way.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor Manufacturing International Corporation (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations in design process technology still need to be overcome. For example, variable capacitors, also known as varactors, are used extensively in mixed signal and RF circuit designs, such as tunable voltage controlled oscillators (VCOs) in multi-frequency carriers. The quality of a varactor is often measured by a ratio of its capacitance to its series resistance, also known as a quality factor (Q). In order to obtain a high Q-factor, the series resistance must be reduced. In addition, the capacitance tuning range of a varactor can be improved with reduced parasitic capacitances.
FIG. 1 is a top-view diagram of a conventional finger-type MOS varactor 100. As shown, varactor 100 includes an active region 110 in a substrate, and contacts such as 115 formed in the active region. Varactor 100 also includes polysilicon gate 120 and a number of contacts, such as 125, formed on the polysilicon gate. The capacitance is provided by an MOS capacitor such as 140 where a finger-shaped polysilicon gate overlaps the active area with a dielectric layer (not shown) between the polysilicon gate 120 and active region 110.
FIG. 2 is a 3-dimensional-view diagram of a branch of a conventional finger-type MOS varactor. As shown, capacitor 200 includes a semiconductor substrate 210, gate oxide 215, and a polysilicon gate 240 which may represent a finger of a finger-shaped varactor. Source and drain (S/D) regions 220 and 230 are heavily doped to allow contacts to be formed to the substrate. As is known in the art, the small signal capacitance value of an MOS capacitor varies with a change in the voltage applied to its gate. A desired small signal capacitance value is often obtained by applying a suitable bias voltage. However, parasitic resistances and parasitic capacitances associated with an MOS capacitor can degrade its performance as a variable capacitor. In FIG. 2, the effective gate resistance (Rg) is proportional to finger width L while the effective drain resistance (Rd) is proportional to finger length X. As is known in the art, a high resistance value leads to the degradation of the quality factor Q. For example, if X is a constant, the longer the L is, the lower the Q is. Another varactor design consideration is related to parasitic capacitance. The parasitic capacitance between gate and source/drain is proportional to the perimeter where the poly gate is adjacent to the active area. In order to obtain a large capacitance tuning range, a high ratio between a primary capacitance and a parasitic capacitance will be required, which can be interpreted as the ratio between a Poly/AA overlap area and a Poly/AA adjacent perimeter (A/P ratio). The area to perimeter ratio (A/P) can be expressed as follows.(X*L)/(2X+2*L)=X/(2X/L+2).  (Equation 1)
It can be seen from Equation 1 that, if X is a constant, the larger the width L is, the larger the A/P ratio will become. In other words, a large finger width L leads to a low Q factor and a low parasitic capacitance value. Therefore, it is difficult to design a finger-type MOS varactor to achieve both high quality factor and low parasitic capacitance. These and other limitations are described throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for variable capacitor devices is desired.